Regviz

NXP Semiconductors /LPC43xx /CGU /PLL0AUDIO_NP_DIV

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PLL0AUDIO_NP_DIV

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/LPC18xx/CGU/PLL0AUDIO_NP_DIV#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PDEC0RESERVED0NDEC0RESERVED

Description

PLL0AUDIO N/P-divider register

Fields

PDEC

Decoded P-divider coefficient value
RESERVED

Reserved
NDEC

Decoded N-divider coefficient value
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data